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On-chip Phase Locked Loop (PLL) design for clock multiplier in CMOS Monolithic Active Pixel Sensors (MAPS)
In a detector system, clock distribution to sensors must be controlled at a level allowing proper synchronisation. In order to reach theses requirements for the HFT (Heavy Flavor Tracker) upgrade at STAR (Solenoidal Tracker at RHIC), we have proposed to distribute a low frequency clock at 10 MHz whi...
Autores principales: | , , , , , |
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Lenguaje: | eng |
Publicado: |
CERN
2009
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Materias: | |
Acceso en línea: | https://dx.doi.org/10.5170/CERN-2009-006.543 http://cds.cern.ch/record/1235879 |
_version_ | 1780918562488057856 |
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author | Sun, Q Jaaskelainen, K Valin, I Claus, G Hu-Guo, Ch Hu, Yu |
author_facet | Sun, Q Jaaskelainen, K Valin, I Claus, G Hu-Guo, Ch Hu, Yu |
author_sort | Sun, Q |
collection | CERN |
description | In a detector system, clock distribution to sensors must be controlled at a level allowing proper synchronisation. In order to reach theses requirements for the HFT (Heavy Flavor Tracker) upgrade at STAR (Solenoidal Tracker at RHIC), we have proposed to distribute a low frequency clock at 10 MHz which will be multiplied to 160 MHz in each sensor by a PLL. A PLL has been designed for period jitter less than 20 ps rms, low power consumption and manufactured in a 0.35 μm CMOS process. |
id | cern-1235879 |
institution | Organización Europea para la Investigación Nuclear |
language | eng |
publishDate | 2009 |
publisher | CERN |
record_format | invenio |
spelling | cern-12358792019-09-30T06:29:59Zdoi:10.5170/CERN-2009-006.543http://cds.cern.ch/record/1235879engSun, QJaaskelainen, KValin, IClaus, GHu-Guo, ChHu, YuOn-chip Phase Locked Loop (PLL) design for clock multiplier in CMOS Monolithic Active Pixel Sensors (MAPS)Detectors and Experimental TechniquesIn a detector system, clock distribution to sensors must be controlled at a level allowing proper synchronisation. In order to reach theses requirements for the HFT (Heavy Flavor Tracker) upgrade at STAR (Solenoidal Tracker at RHIC), we have proposed to distribute a low frequency clock at 10 MHz which will be multiplied to 160 MHz in each sensor by a PLL. A PLL has been designed for period jitter less than 20 ps rms, low power consumption and manufactured in a 0.35 μm CMOS process.CERNoai:cds.cern.ch:12358792009 |
spellingShingle | Detectors and Experimental Techniques Sun, Q Jaaskelainen, K Valin, I Claus, G Hu-Guo, Ch Hu, Yu On-chip Phase Locked Loop (PLL) design for clock multiplier in CMOS Monolithic Active Pixel Sensors (MAPS) |
title | On-chip Phase Locked Loop (PLL) design for clock multiplier in CMOS Monolithic Active Pixel Sensors (MAPS) |
title_full | On-chip Phase Locked Loop (PLL) design for clock multiplier in CMOS Monolithic Active Pixel Sensors (MAPS) |
title_fullStr | On-chip Phase Locked Loop (PLL) design for clock multiplier in CMOS Monolithic Active Pixel Sensors (MAPS) |
title_full_unstemmed | On-chip Phase Locked Loop (PLL) design for clock multiplier in CMOS Monolithic Active Pixel Sensors (MAPS) |
title_short | On-chip Phase Locked Loop (PLL) design for clock multiplier in CMOS Monolithic Active Pixel Sensors (MAPS) |
title_sort | on-chip phase locked loop (pll) design for clock multiplier in cmos monolithic active pixel sensors (maps) |
topic | Detectors and Experimental Techniques |
url | https://dx.doi.org/10.5170/CERN-2009-006.543 http://cds.cern.ch/record/1235879 |
work_keys_str_mv | AT sunq onchipphaselockedloopplldesignforclockmultiplierincmosmonolithicactivepixelsensorsmaps AT jaaskelainenk onchipphaselockedloopplldesignforclockmultiplierincmosmonolithicactivepixelsensorsmaps AT valini onchipphaselockedloopplldesignforclockmultiplierincmosmonolithicactivepixelsensorsmaps AT clausg onchipphaselockedloopplldesignforclockmultiplierincmosmonolithicactivepixelsensorsmaps AT huguoch onchipphaselockedloopplldesignforclockmultiplierincmosmonolithicactivepixelsensorsmaps AT huyu onchipphaselockedloopplldesignforclockmultiplierincmosmonolithicactivepixelsensorsmaps |