Charge Pump Clock Generation PLL for the Data Output Block of the Upgraded ATLAS Pixel Front-End in 130 nm CMOS

FE-I4 is the 130 nm ATLAS pixel IC currently under development for upgraded Large Hadron Collider (LHC) luminosities. FE-I4 is based on a low-power analog pixel array and digital architecture concepts tuned to higher hit rates [1]. An integrated Phase Locked Loop (PLL) has been developed that locall...

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Detalles Bibliográficos
Autores principales: Kruth, A, Ahluwalia, G, Arutinov, D, Barbero, M, Gronewald, M, Hemperek, T, Karagounis, M, Krueger, H, Wermes, N, Fougeron, D, Menouni, M, Beccherle, R, Dube, S, Ellege, D, Garcia-Sciveres, M, Gnani, D, Mekkaoui, A, Gromov, V, Kluit, R, Schipper, J
Lenguaje:eng
Publicado: CERN 2009
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.5170/CERN-2009-006.548
http://cds.cern.ch/record/1235880

Internet

https://dx.doi.org/10.5170/CERN-2009-006.548
http://cds.cern.ch/record/1235880

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