Study of FPGA and GPU based pixel calibration for ATLAS IBL

The insertable B-layer (IBL) is a new stage of the ATLAS pixel detector to be installed around 2014. 12 million pixel are attached to new FE-I4 readout ASICs, each controlling 26680 pixel. Compared to the existing FE-I3 based detector the new system features higher readout speed of 160Mbit/s per ASI...

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Detalles Bibliográficos
Autores principales: Dopke, J, Falchieri, D, Flick, T, Gabrielli, A, Grosse-Knetter, J, Krieger, N, Kugel, A, Polini, A, Schroer, N
Lenguaje:eng
Publicado: 2010
Materias:
Detectors and Experimental Techniques
Acceso en línea:http://cds.cern.ch/record/1267377

Internet

http://cds.cern.ch/record/1267377

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