Cargando…
A 4.9-GHz Low Power, Low Jitter, LC Phase Locked Loop
An LC phase locked loop ASIC, fabricated in a commercial 0.25-µm Silicon-on-Sapphire CMOS technology, has been characterized in lab. Random jitter and deterministic jitter are less than 2.5 ps and 10 ps, respectively. The power consumption at 4.9 GHz is 218 mW. The measured tuning range, from 4.7 to...
| Autor principal: | |
|---|---|
| Lenguaje: | eng |
| Publicado: |
2010
|
| Materias: | |
| Acceso en línea: | http://cds.cern.ch/record/1292777 |