A 4.9-GHz Low Power, Low Jitter, LC Phase Locked Loop

An LC phase locked loop ASIC, fabricated in a commercial 0.25-µm Silicon-on-Sapphire CMOS technology, has been characterized in lab. Random jitter and deterministic jitter are less than 2.5 ps and 10 ps, respectively. The power consumption at 4.9 GHz is 218 mW. The measured tuning range, from 4.7 to 5.0 GHz, is narrower than the simulated values of from 3.8 to 5.0 GHz. The narrow tuning range has been investigated and traced to the first stage of the divider. This will be corrected in the next submission.