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The Design for Test Architecture in Digital Section of the ATLAS FE-I4 Chip
This paper describes an original Design-for-Test (DfT) architecture implemented in FE-I4 pixel readout System-on-Chip (Soc) to accommodate the higher quality demands of future generation LHC detectors. To ensure that as high number of devices as possible is used during the experiment, the so-called...
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| Lenguaje: | eng |
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2010
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| Acceso en línea: | http://cds.cern.ch/record/1295233 |