The Design for Test Architecture in Digital Section of the ATLAS FE-I4 Chip

This paper describes an original Design-for-Test (DfT) architecture implemented in FE-I4 pixel readout System-on-Chip (Soc) to accommodate the higher quality demands of future generation LHC detectors. To ensure that as high number of devices as possible is used during the experiment, the so-called production test to detect faulty devices after the manufacturing has to be executed. For that reason, we devised a straightforward and efficient DfT circuitry inside the FE-I4 that will enable high fault coverage of potential structural faults while maintaining the performance and area penalties negligible.