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Design and Verification of Digital Architecture of 65K Pixel Readout Chip for High-Energy Physics
The feasibility to design and implement a front-end ASIC for the upgrade of the VELO detector of LHCb experiment at CERN using IBM’s 130nm standard CMOS process and a standard cell library is studied in this thesis. The proposed architecture is a design to cope with high data rates and continuous da...
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| Lenguaje: | eng |
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University of Turku
2010
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| Acceso en línea: | http://cds.cern.ch/record/1298267 |