Cargando…
Writing testbenches using System Verilog
Verification is too often approached in an ad hoc fashion. Moore's Law demands a productivity revolution in functional verification methodology. This work offers functional verification features that were added to the Verilog language as part of SystemVerilog. It introduces the reader to the el...
| Autor principal: | |
|---|---|
| Lenguaje: | eng |
| Publicado: |
Springer
2006
|
| Materias: | |
| Acceso en línea: | http://cds.cern.ch/record/1354941 |