Optimizing latency in Xilinx FPGA implementations of the GBT

The GigaBit Transceiver (GBT) {[}1] system has been developed to replace the Timing, Trigger and Control (TTC) system {[}2], currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, desi...

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Detalles Bibliográficos
Autores principales: Muschter, S, Soos, C, Bohm, C, Cachemiche, J-P, Baron, S
Lenguaje:eng
Publicado: 2010
Materias:
Engineering
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/5/12/C12017
https://dx.doi.org/10.1088/1748-0221/6/05/E05001
http://cds.cern.ch/record/1359249

Internet

https://dx.doi.org/10.1088/1748-0221/5/12/C12017
https://dx.doi.org/10.1088/1748-0221/6/05/E05001
http://cds.cern.ch/record/1359249

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