An FPGA based Topological Processor Prototype for the ATLAS Level-1 Trigger Upgrade

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By 2014 the LHC will collide proton bunches at 14 TeV with an increased instantaneous luminosity up to 3×10^34cm−2s−1. A reduction on the trigger rate can be achieved by applying topological cuts adopting a new FPGA based module in the L1 trigger: the Topological Processor (TP). This presentation fo...

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Detalles Bibliográficos
Autores principales: "Wenzel, V, "Bauss, B, "Buescher, V, "Degele, R, "Ji, W, "Moritz, S, "Reiss, A, "Schaefer, U, "Simioni, E, "Tapprogge, S
Lenguaje:eng
Publicado: 2012
Materias:
Detectors and Experimental Techniques
Acceso en línea:http://cds.cern.ch/record/1478361

Internet

http://cds.cern.ch/record/1478361

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