An FPGA based Topological Processor Prototype for the ATLAS Level-1 Trigger Upgrade

By 2014 the LHC will collide proton bunches at 14 TeV with an increased instantaneous luminosity up to 3×10^34cm−2s−1. A reduction on the trigger rate can be achieved by applying topological cuts adopting a new FPGA based module in the L1 trigger: the Topological Processor (TP). This presentation focuses on the design of the first TP prototype and on the test results on algorithm implemented in the TP demonstrator in order to measure latency and FPGA logic utilization.