An FPGA based Topological Processor Prototype for the ATLAS Level-1 Trigger Upgrade

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By 2014 the LHC will collide proton bunches at 14 TeV with an increased instantaneous luminosity up to 3×10^34cm−2s−1. A reduction on the trigger rate can be achieved by applying topological cuts adopting a new FPGA based module in the L1 trigger: the Topological Processor (TP). This presentation fo...

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Autores principales: "Wenzel, V, "Bauss, B, "Buescher, V, "Degele, R, "Ji, W, "Moritz, S, "Reiss, A, "Schaefer, U, "Simioni, E, "Tapprogge, S
Lenguaje:eng
Publicado: 2012
Materias:
Detectors and Experimental Techniques
Acceso en línea:http://cds.cern.ch/record/1478361
_version_ 1780925595320844288
author "Wenzel, V
"Bauss, B
"Buescher, V
"Degele, R
"Ji, W
"Moritz, S
"Reiss, A
"Schaefer, U
"Simioni, E
"Tapprogge, S
author_facet "Wenzel, V
"Bauss, B
"Buescher, V
"Degele, R
"Ji, W
"Moritz, S
"Reiss, A
"Schaefer, U
"Simioni, E
"Tapprogge, S
author_sort "Wenzel, V
collection CERN
description By 2014 the LHC will collide proton bunches at 14 TeV with an increased instantaneous luminosity up to 3×10^34cm−2s−1. A reduction on the trigger rate can be achieved by applying topological cuts adopting a new FPGA based module in the L1 trigger: the Topological Processor (TP). This presentation focuses on the design of the first TP prototype and on the test results on algorithm implemented in the TP demonstrator in order to measure latency and FPGA logic utilization.
id cern-1478361
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2012
record_format invenio
spelling cern-14783612019-09-30T06:29:59Zhttp://cds.cern.ch/record/1478361eng"Wenzel, V"Bauss, B"Buescher, V"Degele, R"Ji, W"Moritz, S"Reiss, A"Schaefer, U"Simioni, E"Tapprogge, SAn FPGA based Topological Processor Prototype for the ATLAS Level-1 Trigger UpgradeDetectors and Experimental TechniquesBy 2014 the LHC will collide proton bunches at 14 TeV with an increased instantaneous luminosity up to 3×10^34cm−2s−1. A reduction on the trigger rate can be achieved by applying topological cuts adopting a new FPGA based module in the L1 trigger: the Topological Processor (TP). This presentation focuses on the design of the first TP prototype and on the test results on algorithm implemented in the TP demonstrator in order to measure latency and FPGA logic utilization.ATL-DAQ-SLIDE-2012-529oai:cds.cern.ch:14783612012-09-17
spellingShingle Detectors and Experimental Techniques
"Wenzel, V
"Bauss, B
"Buescher, V
"Degele, R
"Ji, W
"Moritz, S
"Reiss, A
"Schaefer, U
"Simioni, E
"Tapprogge, S
An FPGA based Topological Processor Prototype for the ATLAS Level-1 Trigger Upgrade
title An FPGA based Topological Processor Prototype for the ATLAS Level-1 Trigger Upgrade
title_full An FPGA based Topological Processor Prototype for the ATLAS Level-1 Trigger Upgrade
title_fullStr An FPGA based Topological Processor Prototype for the ATLAS Level-1 Trigger Upgrade
title_full_unstemmed An FPGA based Topological Processor Prototype for the ATLAS Level-1 Trigger Upgrade
title_short An FPGA based Topological Processor Prototype for the ATLAS Level-1 Trigger Upgrade
title_sort fpga based topological processor prototype for the atlas level-1 trigger upgrade
topic Detectors and Experimental Techniques
url http://cds.cern.ch/record/1478361
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