Implementation and Tests of FPGA-embedded PowerPC in the control system of the ATLAS IBL ROD card

The Insertable B-layer project is planned for the upgrade of the ATLAS experiment at LHC. A silicon layer will be inserted into the existing Pixel Detector together with new electronics. The readout off-detector system is implemented with a Back-Of-Crate module implementing I/O functionality and a R...

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Detalles Bibliográficos
Autores principales: Balbi, G, Bindi, M, Falchieri, D, Gabrielli, A, Furini, M, Kugel, A, Travaglini, R, Wensing, M
Lenguaje:eng
Publicado: 2012
Materias:
Detectors and Experimental Techniques
Acceso en línea:http://cds.cern.ch/record/1493321

Internet

http://cds.cern.ch/record/1493321

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