Implementation and Tests of FPGA-embedded PowerPC in the control system of the ATLAS IBL ROD card

The Insertable B-layer project is planned for the upgrade of the ATLAS experiment at LHC. A silicon layer will be inserted into the existing Pixel Detector together with new electronics. The readout off-detector system is implemented with a Back-Of-Crate module implementing I/O functionality and a R...

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Detalles Bibliográficos
Autores principales: Balbi, G, Bindi, M, Falchieri, D, Gabrielli, A, Furini, M, Kugel, A, Travaglini, R, Wensing, M
Lenguaje:eng
Publicado: 2012
Materias:
Detectors and Experimental Techniques
Acceso en línea:http://cds.cern.ch/record/1493321
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author Balbi, G
Bindi, M
Falchieri, D
Gabrielli, A
Furini, M
Kugel, A
Travaglini, R
Wensing, M
author_facet Balbi, G
Bindi, M
Falchieri, D
Gabrielli, A
Furini, M
Kugel, A
Travaglini, R
Wensing, M
author_sort Balbi, G
collection CERN
description The Insertable B-layer project is planned for the upgrade of the ATLAS experiment at LHC. A silicon layer will be inserted into the existing Pixel Detector together with new electronics. The readout off-detector system is implemented with a Back-Of-Crate module implementing I/O functionality and a Readout-Driver card (ROD) for data processing. The ROD hosts the electronics devoted to control operations implemented both with a back- compatible solution (via DSP) and with a PowerPC embedded into an FPGA. In this document major firmware and software achievements concerning the PowerPC implementation, tested on ROD prototypes, will be reported.
id cern-1493321
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2012
record_format invenio
spelling cern-14933212019-09-30T06:29:59Zhttp://cds.cern.ch/record/1493321engBalbi, GBindi, MFalchieri, DGabrielli, AFurini, MKugel, ATravaglini, RWensing, MImplementation and Tests of FPGA-embedded PowerPC in the control system of the ATLAS IBL ROD cardDetectors and Experimental TechniquesThe Insertable B-layer project is planned for the upgrade of the ATLAS experiment at LHC. A silicon layer will be inserted into the existing Pixel Detector together with new electronics. The readout off-detector system is implemented with a Back-Of-Crate module implementing I/O functionality and a Readout-Driver card (ROD) for data processing. The ROD hosts the electronics devoted to control operations implemented both with a back- compatible solution (via DSP) and with a PowerPC embedded into an FPGA. In this document major firmware and software achievements concerning the PowerPC implementation, tested on ROD prototypes, will be reported.ATL-INDET-PROC-2012-026oai:cds.cern.ch:14933212012-11-12
spellingShingle Detectors and Experimental Techniques
Balbi, G
Bindi, M
Falchieri, D
Gabrielli, A
Furini, M
Kugel, A
Travaglini, R
Wensing, M
Implementation and Tests of FPGA-embedded PowerPC in the control system of the ATLAS IBL ROD card
title Implementation and Tests of FPGA-embedded PowerPC in the control system of the ATLAS IBL ROD card
title_full Implementation and Tests of FPGA-embedded PowerPC in the control system of the ATLAS IBL ROD card
title_fullStr Implementation and Tests of FPGA-embedded PowerPC in the control system of the ATLAS IBL ROD card
title_full_unstemmed Implementation and Tests of FPGA-embedded PowerPC in the control system of the ATLAS IBL ROD card
title_short Implementation and Tests of FPGA-embedded PowerPC in the control system of the ATLAS IBL ROD card
title_sort implementation and tests of fpga-embedded powerpc in the control system of the atlas ibl rod card
topic Detectors and Experimental Techniques
url http://cds.cern.ch/record/1493321
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