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Design of the 65 nm CLICpix demonstrator chip
A hybrid pixel detector ASIC designed to be used in the vertex detector for the CLIC experiment is presented in this note. It has been designed using a commercial 65 nm CMOS technology. The main features include simultaneous 4-bit TOT and TOA measurements with 10 ns accuracy, a spatial resolution of...
| Autores principales: | , , |
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| Lenguaje: | eng |
| Publicado: |
2012
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| Materias: | |
| Acceso en línea: | http://cds.cern.ch/record/1507691 |