Design of the 65 nm CLICpix demonstrator chip

A hybrid pixel detector ASIC designed to be used in the vertex detector for the CLIC experiment is presented in this note. It has been designed using a commercial 65 nm CMOS technology. The main features include simultaneous 4-bit TOT and TOA measurements with 10 ns accuracy, a spatial resolution of 3 um (the pixel size is 25x25 um), an on-chip data compression scheme and power pulsing capability. A prototype with a fully featured array of 64 by 64 pixels has been designed and produced. Testing on the prototype is ongoing.