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System-on-chip test architectures: nanometer design for testability
| Autores principales: | , , |
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| Lenguaje: | eng |
| Publicado: |
Morgan Kaufmann Publishers
2008
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| Materias: | |
| Acceso en línea: | http://cds.cern.ch/record/1512028 |
| _version_ | 1780928028416671744 |
|---|---|
| author | Wang, Laung-Terng Stroud, Charles E Touba, Nur A |
| author_facet | Wang, Laung-Terng Stroud, Charles E Touba, Nur A |
| author_sort | Wang, Laung-Terng |
| collection | CERN |
| id | cern-1512028 |
| institution | Organización Europea para la Investigación Nuclear |
| language | eng |
| publishDate | 2008 |
| publisher | Morgan Kaufmann Publishers |
| record_format | invenio |
| spelling | cern-15120282021-04-21T23:32:14Zhttp://cds.cern.ch/record/1512028engWang, Laung-TerngStroud, Charles ETouba, Nur ASystem-on-chip test architectures: nanometer design for testability Computing and ComputersMorgan Kaufmann Publishersoai:cds.cern.ch:15120282008 |
| spellingShingle | Computing and Computers Wang, Laung-Terng Stroud, Charles E Touba, Nur A System-on-chip test architectures: nanometer design for testability |
| title | System-on-chip test architectures: nanometer design for testability |
| title_full | System-on-chip test architectures: nanometer design for testability |
| title_fullStr | System-on-chip test architectures: nanometer design for testability |
| title_full_unstemmed | System-on-chip test architectures: nanometer design for testability |
| title_short | System-on-chip test architectures: nanometer design for testability |
| title_sort | system-on-chip test architectures: nanometer design for testability |
| topic | Computing and Computers |
| url | http://cds.cern.ch/record/1512028 |
| work_keys_str_mv | AT wanglaungterng systemonchiptestarchitecturesnanometerdesignfortestability AT stroudcharlese systemonchiptestarchitecturesnanometerdesignfortestability AT toubanura systemonchiptestarchitecturesnanometerdesignfortestability |