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Verification methodology manual for SystemVerilog

SystemVerilog is a unified language that serves both design and verification engineers by including RTL design constructs, assertions and a rich set of verification constructs. This book is based upon best verification practices by ARM, Synopsys and their customers. It is useful for those involved i...

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Detalles Bibliográficos
Autores principales: Bergeron, Janick, Cerny, Eduard, Hunter, Alan
Lenguaje:eng
Publicado: Springer 2006
Materias:
Acceso en línea:http://cds.cern.ch/record/1607410