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The Gm/Id methodology, a sizing tool for low-voltage analog CMOS circuits
IC designers appraise currently MOS transistor geometries and currents to compromise objectives like gain-bandwidth, slew-rate, dynamic range, noise, non-linear distortion, etc. Making optimal choices is a difficult task. How to minimize for instance the power consumption of an operational amplifier...
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| Lenguaje: | eng |
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Springer
2009
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| Acceso en línea: | http://cds.cern.ch/record/1610053 |