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NaNet:a low-latency NIC enabling GPU-based, real-time low level trigger systems

We implemented the NaNet FPGA-based PCI2 Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input data stream from its GbE interface and redirect it, without any intermediate buffering or CPU intervention, to the memory...

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Autores principales: Ammendola, Roberto, Biagioni, Andrea, Fantechi, Riccardo, Frezza, Ottorino, Lamanna, Gianluca, Lo Cicero, Francesca, Lonardo, Alessandro, Paolucci, Pier Stanislao, Pantaleo, Felice, Piandani, Roberto, Pontisso, Luca, Rossetti, Davide, Simula, Francesco, Sozzi, Marco, Tosoratto, Laura, Vicini, Piero
Lenguaje:eng
Publicado: 2013
Materias:
Acceso en línea:https://dx.doi.org/10.1088/1742-6596/513/1/012018
http://cds.cern.ch/record/1624541
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author Ammendola, Roberto
Biagioni, Andrea
Fantechi, Riccardo
Frezza, Ottorino
Lamanna, Gianluca
Lo Cicero, Francesca
Lonardo, Alessandro
Paolucci, Pier Stanislao
Pantaleo, Felice
Piandani, Roberto
Pontisso, Luca
Rossetti, Davide
Simula, Francesco
Sozzi, Marco
Tosoratto, Laura
Vicini, Piero
author_facet Ammendola, Roberto
Biagioni, Andrea
Fantechi, Riccardo
Frezza, Ottorino
Lamanna, Gianluca
Lo Cicero, Francesca
Lonardo, Alessandro
Paolucci, Pier Stanislao
Pantaleo, Felice
Piandani, Roberto
Pontisso, Luca
Rossetti, Davide
Simula, Francesco
Sozzi, Marco
Tosoratto, Laura
Vicini, Piero
author_sort Ammendola, Roberto
collection CERN
description We implemented the NaNet FPGA-based PCI2 Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input data stream from its GbE interface and redirect it, without any intermediate buffering or CPU intervention, to the memory of a Fermi/Kepler GPU hosted on the same PCIe bus, provided that the two devices share the same upstream root complex. Synthetic benchmarks for latency and bandwidth are presented. We describe how NaNet can be employed in the prototype of the GPU-based RICH low-level trigger processor of the NA62 CERN experiment, to implement the data link between the TEL62 readout boards and the low level trigger processor. Results for the throughput and latency of the integrated system are presented and discussed.
id cern-1624541
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2013
record_format invenio
spelling cern-16245412023-03-14T19:40:01Zdoi:10.1088/1742-6596/513/1/012018http://cds.cern.ch/record/1624541engAmmendola, RobertoBiagioni, AndreaFantechi, RiccardoFrezza, OttorinoLamanna, GianlucaLo Cicero, FrancescaLonardo, AlessandroPaolucci, Pier StanislaoPantaleo, FelicePiandani, RobertoPontisso, LucaRossetti, DavideSimula, FrancescoSozzi, MarcoTosoratto, LauraVicini, PieroNaNet:a low-latency NIC enabling GPU-based, real-time low level trigger systemsDetectors and Experimental TechniquesWe implemented the NaNet FPGA-based PCI2 Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input data stream from its GbE interface and redirect it, without any intermediate buffering or CPU intervention, to the memory of a Fermi/Kepler GPU hosted on the same PCIe bus, provided that the two devices share the same upstream root complex. Synthetic benchmarks for latency and bandwidth are presented. We describe how NaNet can be employed in the prototype of the GPU-based RICH low-level trigger processor of the NA62 CERN experiment, to implement the data link between the TEL62 readout boards and the low level trigger processor. Results for the throughput and latency of the integrated system are presented and discussed.We implemented the NaNet FPGA-based PCIe Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input data stream from its GbE interface and redirect it, without any intermediate buffering or CPU intervention, to the memory of a Fermi/Kepler GPU hosted on the same PCIe bus, provided that the two devices share the same upstream root complex. Synthetic benchmarks for latency and bandwidth are presented. We describe how NaNet can be employed in the prototype of the GPU-based RICH low-level trigger processor of the NA62 CERN experiment, to implement the data link between the TEL62 readout boards and the low level trigger processor. Results for the throughput and latency of the integrated system are presented and discussed.We implemented the NaNet FPGA-based PCI2 Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input data stream from its GbE interface and redirect it, without any intermediate buffering or CPU intervention, to the memory of a Fermi/Kepler GPU hosted on the same PCIe bus, provided that the two devices share the same upstream root complex. Synthetic benchmarks for latency and bandwidth are presented. We describe how NaNet can be employed in the prototype of the GPU-based RICH low-level trigger processor of the NA62 CERN experiment, to implement the data link between the TEL62 readout boards and the low level trigger processor. Results for the throughput and latency of the integrated system are presented and discussed.arXiv:1311.1010oai:cds.cern.ch:16245412013-11-05
spellingShingle Detectors and Experimental Techniques
Ammendola, Roberto
Biagioni, Andrea
Fantechi, Riccardo
Frezza, Ottorino
Lamanna, Gianluca
Lo Cicero, Francesca
Lonardo, Alessandro
Paolucci, Pier Stanislao
Pantaleo, Felice
Piandani, Roberto
Pontisso, Luca
Rossetti, Davide
Simula, Francesco
Sozzi, Marco
Tosoratto, Laura
Vicini, Piero
NaNet:a low-latency NIC enabling GPU-based, real-time low level trigger systems
title NaNet:a low-latency NIC enabling GPU-based, real-time low level trigger systems
title_full NaNet:a low-latency NIC enabling GPU-based, real-time low level trigger systems
title_fullStr NaNet:a low-latency NIC enabling GPU-based, real-time low level trigger systems
title_full_unstemmed NaNet:a low-latency NIC enabling GPU-based, real-time low level trigger systems
title_short NaNet:a low-latency NIC enabling GPU-based, real-time low level trigger systems
title_sort nanet:a low-latency nic enabling gpu-based, real-time low level trigger systems
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1088/1742-6596/513/1/012018
http://cds.cern.ch/record/1624541
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