A PCIe Gen3 based readout for the LHCb upgrade

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The architecture of the data acquisition system foreseen for the LHCb upgrade, to be installed by 2018, is devised to readout events trigger-less, synchronously with the LHC bunch crossing rate at 40 MHz. Within this approach the readout boards act as a bridge between the front-end electronics and t...

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Detalles Bibliográficos
Autores principales: Bellato, M, Collazuol, G, D’Antone, I, Durante, P, Galli, D, Jost, B, Lax, I, Liu, G, Marconi, U, Neufeld, N, Schwemmer, R, Vagnoni, V
Lenguaje:eng
Publicado: 2013
Materias:
Computing and Computers
Acceso en línea:https://dx.doi.org/10.1088/1742-6596/513/1/012023
http://cds.cern.ch/record/1626795

Internet

https://dx.doi.org/10.1088/1742-6596/513/1/012023
http://cds.cern.ch/record/1626795

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