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A PCIe Gen3 based readout for the LHCb upgrade
The architecture of the data acquisition system foreseen for the LHCb upgrade, to be installed by 2018, is devised to readout events trigger-less, synchronously with the LHC bunch crossing rate at 40 MHz. Within this approach the readout boards act as a bridge between the front-end electronics and t...
| Autores principales: | , , , , , , , , , , , |
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| Lenguaje: | eng |
| Publicado: |
2013
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1088/1742-6596/513/1/012023 http://cds.cern.ch/record/1626795 |
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