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Source-synchronous networks-on-chip: circuit and architectural interconnect modeling
This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how...
| Autores principales: | , , |
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| Lenguaje: | eng |
| Publicado: |
Springer
2014
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1007/978-1-4614-9405-8 http://cds.cern.ch/record/1635093 |