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Design-for-test and test optimization techniques for TSV-based 3D stacked ICs
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge res...
| Autores principales: | , |
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| Lenguaje: | eng |
| Publicado: |
Springer
2014
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| Acceso en línea: | https://dx.doi.org/10.1007/978-3-319-02378-6 http://cds.cern.ch/record/1635105 |