Perspectives of 65 nm CMOS technologies for high performance front-end electronics

The 65 nm CMOS generation is currently being evaluated as a promising solution for the integration of high speed circuits with high functional density in a small pixel. This technology node has specific features, such as new materials introduced to limit the current tunneling through the thin dielectric, that need to be thoroughly investigated. In order to assess how these new physical parameters impact on the device properties, such as noise and radiation hardness, this paper presents and discusses the characterization of 65 nm CMOS transistors, in terms of intrinsic gain, gate leakage current and noise performance, before and after irradiation with g-rays. A comparison with data coming from less scaled technologies is also provided.