3D Interconnection with TSV

3D interconnection with TSVs (through silicon via) allows the construction of quasi-monolithic multi-tier ASICs, a technology which offers many advantages. In addition to increasing the avail- able area the main advantage is in shortening the length of metal connections within the circuitry reducing delays and decreasing power dissipation. For industry 3D interconnection is a possibil- ity to continue Moore’s law, or even improve on it (’more than Moore’) beyond scaling. Though many of these arguments are not really relevant for HEP ASICs or sensors 3D technology still offers some important benefits like the possibility of monolithic devices in heterogeneous tech- nologies or backside connectivity for more efficient I/O (4-side buttable chips). R&D has started, notable the Fermilab’s 3DIC activity, projects converting the ATLAS FEI3 frontend into a 3D device and the WP3 work package of the EU funded AIDA project. Examples of these projects will be discussed.