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Development of scalable frequency and power Phase-Locked Loop in 130nm CMOS technology
The design and measurements results of a prototype very low power Phase-Locked Loop (PLL) ASIC for applications in readout systems of particle physics detectors are presented. The PLL was fabricated in 130 nm CMOS technology. It was designed and simulated for frequency range 10 MHz–3.5 GHz. Four div...
| Autores principales: | , , , , |
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| Formato: | info:eu-repo/semantics/article |
| Lenguaje: | eng |
| Publicado: |
JINST
2014
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1088/1748-0221/9/02/C02006 http://cds.cern.ch/record/1693655 |