A Highly Parallel FPGA Implementation of a 2D-Clustering Algorithm for the ATLAS Fast TracKer (FTK) Processor

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The highly parallel 2D-clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors read out drivers (RODs) at 760Gbps, the full rate of level 1 trigg...

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Detalles Bibliográficos
Autores principales: Kimura, N, Annovi, A, Beretta, M, Gatta, M, Gkaitatzis, S, Iizawa, T, Kordas, K, Korikawa, T, Nikolaidis, N, Petridou, P, Sotiropoulou, C-L, Yorita, K, Volpi, G
Lenguaje:eng
Publicado: 2014
Materias:
Particle Physics - Experiment
Acceso en línea:http://cds.cern.ch/record/1703036

Internet

http://cds.cern.ch/record/1703036

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