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Wafer-level chip-scale packaging: analog and power semiconductor applications

This book presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability, and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The...

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Detalles Bibliográficos
Autores principales: Qu, Shichun, Liu, Yong
Lenguaje:eng
Publicado: Springer 2015
Materias:
Acceso en línea:https://dx.doi.org/10.1007/978-1-4939-1556-9
http://cds.cern.ch/record/1968753
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author Qu, Shichun
Liu, Yong
author_facet Qu, Shichun
Liu, Yong
author_sort Qu, Shichun
collection CERN
description This book presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability, and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials, and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical, and stress modeling methodologies is also provided. This book also: ·         Covers the development of wafer-level power discrete packaging with regular wafer-level design concepts and directly bumping technology ·         Introduces the development of the analog and power SIP/3D/TSV/stack die packaging technology ·         Presents the wafer-level analog IC packaging design through fan-in and fan-out with RDLs
id cern-1968753
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2015
publisher Springer
record_format invenio
spelling cern-19687532021-04-21T20:49:52Zdoi:10.1007/978-1-4939-1556-9http://cds.cern.ch/record/1968753engQu, ShichunLiu, YongWafer-level chip-scale packaging: analog and power semiconductor applicationsEngineeringThis book presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability, and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials, and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical, and stress modeling methodologies is also provided. This book also: ·         Covers the development of wafer-level power discrete packaging with regular wafer-level design concepts and directly bumping technology ·         Introduces the development of the analog and power SIP/3D/TSV/stack die packaging technology ·         Presents the wafer-level analog IC packaging design through fan-in and fan-out with RDLsSpringeroai:cds.cern.ch:19687532015
spellingShingle Engineering
Qu, Shichun
Liu, Yong
Wafer-level chip-scale packaging: analog and power semiconductor applications
title Wafer-level chip-scale packaging: analog and power semiconductor applications
title_full Wafer-level chip-scale packaging: analog and power semiconductor applications
title_fullStr Wafer-level chip-scale packaging: analog and power semiconductor applications
title_full_unstemmed Wafer-level chip-scale packaging: analog and power semiconductor applications
title_short Wafer-level chip-scale packaging: analog and power semiconductor applications
title_sort wafer-level chip-scale packaging: analog and power semiconductor applications
topic Engineering
url https://dx.doi.org/10.1007/978-1-4939-1556-9
http://cds.cern.ch/record/1968753
work_keys_str_mv AT qushichun waferlevelchipscalepackaginganalogandpowersemiconductorapplications
AT liuyong waferlevelchipscalepackaginganalogandpowersemiconductorapplications