SEU tolerant memory design for the ATLAS pixel readout chip
The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DICE latches for which layout approaches are adopted are...
Autores principales: | , , , , , , , , , , , , , , , , , , , , , , , , , , |
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Formato: | info:eu-repo/semantics/article |
Lenguaje: | eng |
Publicado: |
JINST
2013
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Materias: | |
Acceso en línea: | https://dx.doi.org/10.1088/1748-0221/8/02/C02026 http://cds.cern.ch/record/1997618 |