SEU tolerant memory design for the ATLAS pixel readout chip

The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DICE latches for which layout approaches are adopted are...

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Detalles Bibliográficos
Autores principales: Menouni, M, Arutinov, D, Backhaus, M, Barbero, M, Beccherle, R, Breugnon, P, Caminada, L, Dube, S, Darbo, G, Fleury, J, Fougeron, D, Garcia-Sciveres, M, Gensolen, F, Gnani, D, Gonella, L, Gromov, V, Hemperek, T, Jensen, F, karagounis, M, Kluit, R, Krüger, G, Kruth, A, Lu, Y, Mekkaoui, A, Rozanov, A, Schipper, J.D, Zivkovic, V
Formato: info:eu-repo/semantics/article
Lenguaje:eng
Publicado: JINST 2013
Materias:
Detectors and Experimental Techniques
3: Microelectronics and interconnection technology
3.3: Shareable IP Blocks for HEP
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/8/02/C02026
http://cds.cern.ch/record/1997618

Internet

https://dx.doi.org/10.1088/1748-0221/8/02/C02026
http://cds.cern.ch/record/1997618

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