Digital column readout architectures for hybrid pixel detector readout chips

In this paper, two digital column architectures suitable for sparse readout of data from a pixel matrix in trigger-less applications are presented. Each architecture reads out a pixel matrix of 256 x 256 pixels with a pixel pitch of 55 µm. The first architecture has been implemented in the Timepix3...

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Detalles Bibliográficos
Autores principales: Poikela, T, Plosila, J, Westerlund, T, Buytaert, J, Campbell, M, De Gaspari, M, Llopart, X, Wyllie, K, Gromov, V, Kluit, R, van Beuzekom, M, Zappon, F, Zivkovic, V, Brezina, C, Desch, K, Fu, Y, Kruth, A
Formato: info:eu-repo/semantics/article
Lenguaje:eng
Publicado: JINST 2014
Materias:
Detectors and Experimental Techniques
9: Advanced infrastructures for detector R&D
9.2: Gaseous Detector Facilities
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/9/01/C01007
http://cds.cern.ch/record/1997649

Internet

https://dx.doi.org/10.1088/1748-0221/9/01/C01007
http://cds.cern.ch/record/1997649

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