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Advanced verification topics
The Accellera Universal Verification Methodology (UVM) standard is architected to scale, but verification is growing and in more than just the digital design dimension. It is growing in the SoC dimension to include low-power and mixed-signal and the system integration dimension to include multi-lang...
| Autores principales: | , , , , , , , |
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| Lenguaje: | eng |
| Publicado: |
Cadence Design Systems
2011
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| Materias: | |
| Acceso en línea: | http://cds.cern.ch/record/2025473 |