Cargando…

Advanced verification topics

The Accellera Universal Verification Methodology (UVM) standard is architected to scale, but verification is growing and in more than just the digital design dimension. It is growing in the SoC dimension to include low-power and mixed-signal and the system integration dimension to include multi-lang...

Descripción completa

Detalles Bibliográficos
Autores principales: Bhattacharya, Bishnupriya, Decker, John, Hall, Gary, Heaton, Nick, Kashai, Yaron, Khan Neyaz, Kirshenbaum, Zeev, Shneydor, Efrat
Lenguaje:eng
Publicado: Cadence Design Systems 2011
Materias:
Acceso en línea:http://cds.cern.ch/record/2025473
Descripción
Sumario:The Accellera Universal Verification Methodology (UVM) standard is architected to scale, but verification is growing and in more than just the digital design dimension. It is growing in the SoC dimension to include low-power and mixed-signal and the system integration dimension to include multi-language support and acceleration. These items and others all contribute to the quality of the SOC so the Metric-Driven Verification (MDV) methodology is needed to unify it all into a coherent verification plan. This book is for verification engineers and managers familiar with the UVM and the benefits it brings to digital verification but who also need to tackle specialized tasks. It is also written for the SoC project manager that is tasked with building an efficient worldwide team. While the task continues to become more complex, Advanced Verification Topics describes methodologies outside of the Accellera UVM standard, but that build on it, to provide a way for SoC teams to stay productive and profitable.