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Advanced verification topics

The Accellera Universal Verification Methodology (UVM) standard is architected to scale, but verification is growing and in more than just the digital design dimension. It is growing in the SoC dimension to include low-power and mixed-signal and the system integration dimension to include multi-lang...

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Autores principales: Bhattacharya, Bishnupriya, Decker, John, Hall, Gary, Heaton, Nick, Kashai, Yaron, Khan Neyaz, Kirshenbaum, Zeev, Shneydor, Efrat
Lenguaje:eng
Publicado: Cadence Design Systems 2011
Materias:
Acceso en línea:http://cds.cern.ch/record/2025473
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author Bhattacharya, Bishnupriya
Decker, John
Hall, Gary
Heaton, Nick
Kashai, Yaron
Khan Neyaz
Kirshenbaum, Zeev
Shneydor, Efrat
author_facet Bhattacharya, Bishnupriya
Decker, John
Hall, Gary
Heaton, Nick
Kashai, Yaron
Khan Neyaz
Kirshenbaum, Zeev
Shneydor, Efrat
author_sort Bhattacharya, Bishnupriya
collection CERN
description The Accellera Universal Verification Methodology (UVM) standard is architected to scale, but verification is growing and in more than just the digital design dimension. It is growing in the SoC dimension to include low-power and mixed-signal and the system integration dimension to include multi-language support and acceleration. These items and others all contribute to the quality of the SOC so the Metric-Driven Verification (MDV) methodology is needed to unify it all into a coherent verification plan. This book is for verification engineers and managers familiar with the UVM and the benefits it brings to digital verification but who also need to tackle specialized tasks. It is also written for the SoC project manager that is tasked with building an efficient worldwide team. While the task continues to become more complex, Advanced Verification Topics describes methodologies outside of the Accellera UVM standard, but that build on it, to provide a way for SoC teams to stay productive and profitable.
id cern-2025473
institution Organización Europea para la Investigación Nuclear
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publishDate 2011
publisher Cadence Design Systems
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spelling cern-20254732021-04-21T20:11:04Zhttp://cds.cern.ch/record/2025473engBhattacharya, BishnupriyaDecker, JohnHall, GaryHeaton, NickKashai, YaronKhan NeyazKirshenbaum, ZeevShneydor, EfratAdvanced verification topicsEngineeringThe Accellera Universal Verification Methodology (UVM) standard is architected to scale, but verification is growing and in more than just the digital design dimension. It is growing in the SoC dimension to include low-power and mixed-signal and the system integration dimension to include multi-language support and acceleration. These items and others all contribute to the quality of the SOC so the Metric-Driven Verification (MDV) methodology is needed to unify it all into a coherent verification plan. This book is for verification engineers and managers familiar with the UVM and the benefits it brings to digital verification but who also need to tackle specialized tasks. It is also written for the SoC project manager that is tasked with building an efficient worldwide team. While the task continues to become more complex, Advanced Verification Topics describes methodologies outside of the Accellera UVM standard, but that build on it, to provide a way for SoC teams to stay productive and profitable.Cadence Design Systemsoai:cds.cern.ch:20254732011
spellingShingle Engineering
Bhattacharya, Bishnupriya
Decker, John
Hall, Gary
Heaton, Nick
Kashai, Yaron
Khan Neyaz
Kirshenbaum, Zeev
Shneydor, Efrat
Advanced verification topics
title Advanced verification topics
title_full Advanced verification topics
title_fullStr Advanced verification topics
title_full_unstemmed Advanced verification topics
title_short Advanced verification topics
title_sort advanced verification topics
topic Engineering
url http://cds.cern.ch/record/2025473
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AT deckerjohn advancedverificationtopics
AT hallgary advancedverificationtopics
AT heatonnick advancedverificationtopics
AT kashaiyaron advancedverificationtopics
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AT kirshenbaumzeev advancedverificationtopics
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