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Formal verification: an essential toolkit for modern VLSI design
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and present...
| Autores principales: | , , |
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| Lenguaje: | eng |
| Publicado: |
Elsevier Science
2015
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| Materias: | |
| Acceso en línea: | http://cds.cern.ch/record/2043121 |