FPGA Implementation of a Fixed Latency Scheme in a Signal Packet Router for the Upgrade of ATLAS Forward Muon Trigger Electronics

We propose a new fixed latency scheme for Xilinx gigabit transceivers that will be used in the upgrade of the ATLAS forward muon spectrometer at the Large Hadron Collider. The fixed latency scheme is implemented in a 4.8 Gbps link between a frontend data serializer ASIC and a packet router. To achie...

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Autores principales: Wang, Jinhong, Hu, Xueye, Schwarz, Thomas, Zhu, Junjie, Chapman, J.W., Dai, Tiesheng, Zhou, Bing
Lenguaje:eng
Publicado: 2015
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1109/TNS.2015.2477089
http://cds.cern.ch/record/2054711
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author Wang, Jinhong
Hu, Xueye
Schwarz, Thomas
Zhu, Junjie
Chapman, J.W.
Dai, Tiesheng
Zhou, Bing
author_facet Wang, Jinhong
Hu, Xueye
Schwarz, Thomas
Zhu, Junjie
Chapman, J.W.
Dai, Tiesheng
Zhou, Bing
author_sort Wang, Jinhong
collection CERN
description We propose a new fixed latency scheme for Xilinx gigabit transceivers that will be used in the upgrade of the ATLAS forward muon spectrometer at the Large Hadron Collider. The fixed latency scheme is implemented in a 4.8 Gbps link between a frontend data serializer ASIC and a packet router. To achieve fixed latency, we use IO delay and dedicated carry in resources in a Xilinx FPGA, while minimally relying on the embedded features of the FPGA transceivers. The scheme is protocol independent and can be adapted to FPGA from other vendors with similar resources. This paper presents a detailed implementation of the fixed latency scheme, as well as simulations of the real environment in the ATLAS forward muon region.
id cern-2054711
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2015
record_format invenio
spelling cern-20547112023-03-14T16:54:47Zdoi:10.1109/TNS.2015.2477089http://cds.cern.ch/record/2054711engWang, JinhongHu, XueyeSchwarz, ThomasZhu, JunjieChapman, J.W.Dai, TieshengZhou, BingFPGA Implementation of a Fixed Latency Scheme in a Signal Packet Router for the Upgrade of ATLAS Forward Muon Trigger ElectronicsDetectors and Experimental TechniquesWe propose a new fixed latency scheme for Xilinx gigabit transceivers that will be used in the upgrade of the ATLAS forward muon spectrometer at the Large Hadron Collider. The fixed latency scheme is implemented in a 4.8 Gbps link between a frontend data serializer ASIC and a packet router. To achieve fixed latency, we use IO delay and dedicated carry in resources in a Xilinx FPGA, while minimally relying on the embedded features of the FPGA transceivers. The scheme is protocol independent and can be adapted to FPGA from other vendors with similar resources. This paper presents a detailed implementation of the fixed latency scheme, as well as simulations of the real environment in the ATLAS forward muon region.We propose a new fixed latency scheme for Xilinx gigabit transceivers that will be used in the upgrade of the ATLAS forward muon spectrometer at the Large Hadron Collider. The fixed latency scheme is implemented in a 4.8 Gbps link between a frontend data serializer ASIC and a packet router. To achieve fixed latency, we use IO delay and dedicated carry in resources in a Xilinx FPGA, while minimally relying on the embedded features of the FPGA transceivers. The scheme is protocol independent and can be adapted to FPGA from other vendors with similar resources. This paper presents a detailed implementation of the fixed latency scheme, as well as simulations of the real environment in the ATLAS forward muon region.arXiv:1509.06637oai:cds.cern.ch:20547112015-09-20
spellingShingle Detectors and Experimental Techniques
Wang, Jinhong
Hu, Xueye
Schwarz, Thomas
Zhu, Junjie
Chapman, J.W.
Dai, Tiesheng
Zhou, Bing
FPGA Implementation of a Fixed Latency Scheme in a Signal Packet Router for the Upgrade of ATLAS Forward Muon Trigger Electronics
title FPGA Implementation of a Fixed Latency Scheme in a Signal Packet Router for the Upgrade of ATLAS Forward Muon Trigger Electronics
title_full FPGA Implementation of a Fixed Latency Scheme in a Signal Packet Router for the Upgrade of ATLAS Forward Muon Trigger Electronics
title_fullStr FPGA Implementation of a Fixed Latency Scheme in a Signal Packet Router for the Upgrade of ATLAS Forward Muon Trigger Electronics
title_full_unstemmed FPGA Implementation of a Fixed Latency Scheme in a Signal Packet Router for the Upgrade of ATLAS Forward Muon Trigger Electronics
title_short FPGA Implementation of a Fixed Latency Scheme in a Signal Packet Router for the Upgrade of ATLAS Forward Muon Trigger Electronics
title_sort fpga implementation of a fixed latency scheme in a signal packet router for the upgrade of atlas forward muon trigger electronics
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1109/TNS.2015.2477089
http://cds.cern.ch/record/2054711
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