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Design and test performance of the ATLAS Feature Extractor trigger boards for the Phase-1 Upgrade

In Run 3, the ATLAS Level-1 Calorimeter Trigger will be augmented by an Electron Feature Extractor (eFEX), to identify isolated e/g and particles, and a Jet Feature Extractor (jFEX), to identify energetic jets and calculate various local energy sums. Each module accommodates more than 450 differenti...

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Autor principal: Qian, Weiming
Lenguaje:eng
Publicado: 2016
Materias:
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/12/01/C01079
http://cds.cern.ch/record/2230003
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author Qian, Weiming
author_facet Qian, Weiming
author_sort Qian, Weiming
collection CERN
description In Run 3, the ATLAS Level-1 Calorimeter Trigger will be augmented by an Electron Feature Extractor (eFEX), to identify isolated e/g and particles, and a Jet Feature Extractor (jFEX), to identify energetic jets and calculate various local energy sums. Each module accommodates more than 450 differential signals that can operate at up to 12.8 Gb/s, some of which are routed over 30 cm between FPGAs. Presented here are the module designs, the processes that have been adopted to meet the challenges associated with multi-Gb/s PCB design, and the results of tests that characterize the performance of these modules.
id cern-2230003
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2016
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spelling cern-22300032019-09-30T06:29:59Zdoi:10.1088/1748-0221/12/01/C01079http://cds.cern.ch/record/2230003engQian, WeimingDesign and test performance of the ATLAS Feature Extractor trigger boards for the Phase-1 UpgradeParticle Physics - ExperimentIn Run 3, the ATLAS Level-1 Calorimeter Trigger will be augmented by an Electron Feature Extractor (eFEX), to identify isolated e/g and particles, and a Jet Feature Extractor (jFEX), to identify energetic jets and calculate various local energy sums. Each module accommodates more than 450 differential signals that can operate at up to 12.8 Gb/s, some of which are routed over 30 cm between FPGAs. Presented here are the module designs, the processes that have been adopted to meet the challenges associated with multi-Gb/s PCB design, and the results of tests that characterize the performance of these modules.ATL-DAQ-PROC-2016-024oai:cds.cern.ch:22300032016-11-05
spellingShingle Particle Physics - Experiment
Qian, Weiming
Design and test performance of the ATLAS Feature Extractor trigger boards for the Phase-1 Upgrade
title Design and test performance of the ATLAS Feature Extractor trigger boards for the Phase-1 Upgrade
title_full Design and test performance of the ATLAS Feature Extractor trigger boards for the Phase-1 Upgrade
title_fullStr Design and test performance of the ATLAS Feature Extractor trigger boards for the Phase-1 Upgrade
title_full_unstemmed Design and test performance of the ATLAS Feature Extractor trigger boards for the Phase-1 Upgrade
title_short Design and test performance of the ATLAS Feature Extractor trigger boards for the Phase-1 Upgrade
title_sort design and test performance of the atlas feature extractor trigger boards for the phase-1 upgrade
topic Particle Physics - Experiment
url https://dx.doi.org/10.1088/1748-0221/12/01/C01079
http://cds.cern.ch/record/2230003
work_keys_str_mv AT qianweiming designandtestperformanceoftheatlasfeatureextractortriggerboardsforthephase1upgrade