Cargando…

TID Tolerance of commercial 130nm CMOS Technologies for HEP experiments

Detalles Bibliográficos
Autor principal:	Gonella, Laura
Lenguaje:	eng
Publicado:	2017
Materias:	Detectors and Experimental Techniques
Acceso en línea:	http://cds.cern.ch/record/2252791

Ejemplares similares

Total Ionizing Dose effects in 130-nm commercial CMOS technologies for HEP experiments
por: Gonella, L, et al.
Publicado: (2007)

130nm TSMC / GF TID+SEU experience
por: Gonella, Laura, et al.
Publicado: (2020)

Investigation of Scaling and Temperature Effects in Total Ionizing Dose (TID) Experiments in 65 nm CMOS
por: Chevas, Loukas, et al.
Publicado: (2018)

Design and characterization of an SEU-robust register in 130nm CMOS for application in HEP ASICs
por: Bonacini, S
Publicado: (2010)

Comparison of a 65 nm CMOS Ring- and LC-Oscillator Based PLL in Terms of TID and SEU Sensitivity
por: Prinzie, Jeffrey, et al.
Publicado: (2017)

Low-noise design issues for analog front-end electronics in 130 nm and 90 nm CMOS technologies
por: Manghisoni, M, et al.
Publicado: (2007)

Radiation tolerance study of a commercial 65 nm CMOS technology for high energy physics applications
por: Ding, Lili, et al.
Publicado: (2016)

MAPS in 130 nm triple well CMOS technology for HEP applications
por: Pozzati, E, et al.
Publicado: (2007)

A 10 Gb/s laser driver in 130 nm CMOS technology for high energy physics applications
por: Zhang, T, et al.
Publicado: (2015)

Design of the analog front-end for the Timepix3 and Smallpix hybrid pixel detectors in 130 nm CMOS technology
por: Gaspari, M De, et al.
Publicado: (2014)

Radiation hardness studies of a 130 nm Silicon Germanium BiCMOS technology with a dedicated ASIC
por: Díez, S, et al.
Publicado: (2009)

Developments of two 4 × 10 Gb/s VCSEL array drivers in 65 nm CMOS for HEP experiments
por: Guo, D, et al.
Publicado: (2017)

An 8-Channel ASD in 130 nm CMOS for ATLAS Muon Drift Tube Readout at the HL-LHC
por: Fras, Markus, et al.
Publicado: (2018)

10-Gb/s Distributed Amplifier-Based VCSEL Driver IC With ESD Protection in 130-nm CMOS
por: Zhang, Tao, et al.
Publicado: (2016)

Single Event Gate Rupture in 130-nm CMOS Transistor Arrays Subjected to X-Ray Irradiation
por: Silvestri, M, et al.
Publicado: (2010)

TID and SEU performance of a commercial 013 $\mu$ m CMOS technology
por: Hänsler, Kurt, et al.
Publicado: (2004)

65 nm Technology for HEP: Status and Perspective
por: Valerio, Pierpaolo
Publicado: (2015)

Characterization and Modeling of Gigarad-TID-Induced Drain Leakage Current of 28-nm Bulk MOSFETs
por: Zhang, Chun-Min, et al.
Publicado: (2018)

Radiation-Tolerant Digitally Controlled Ring Oscillator in 65-nm CMOS
por: Biereigel, Stefan, et al.
Publicado: (2022)

Prototype Active Silicon Sensor in 150 nm HR-CMOS Technology for ATLAS Inner Detector Upgrade
por: Rymaszewski, Piotr, et al.
Publicado: (2016)

Development of front-end electronics for LumiCal detector in CMOS 130 nm technology
por: Moron, J, et al.
Publicado: (2015)

Development of front-end electronics for LumiCal detector in CMOS 130 nm technology
por: Firlej, M, et al.
Publicado: (2015)

An 8-channel programmable 80/160/320 Mbit/s radiation-hard phase-aligner circuit in 130-nm CMOS
por: Tavernier, F, et al.
Publicado: (2012)

Development of scalable frequency and power Phase-Locked Loop in 130nm CMOS technology
por: Firlej, M, et al.
Publicado: (2014)

Charge Pump Clock Generation PLL for the Data Output Block of the Upgraded ATLAS Pixel Front-End in 130 nm CMOS
por: Kruth, A, et al.
Publicado: (2009)

A radiation-hard PLL for frequency multiplication with programmable input clock and phase-selectable output signals in 130 nm CMOS
por: Poltorak, K, et al.
Publicado: (2012)

Depleted Monolithic Active Pixel Sensors in the LFoundry 150 nm and TowerJazz 180 nm CMOS Technologies
por: Wang, T, et al.
Publicado: (2020)

Characterization of irradiated passive CMOS sensors for tracking in HEP experiments
por: Glessgen, Franz Jacob
Publicado: (2022)

Plans for the evaluation of the TID tolerance in 65nm and below
por: Faccio, Federico
Publicado: (2018)

Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade
por: Wang, T., et al.
Publicado: (2016)

Design of large scale sensors in 180 nm CMOS process modified for radiation tolerance
por: Flores Sanz de Acedo, L, et al.
Publicado: (2020)

Characterization of a commercial 65 nm CMOS technology for SLHC applications
por: Bonacini, S, et al.
Publicado: (2012)

Validation tests of the CMS TIB/TID structures
por: D'Alfonso, Mariarosaria, et al.
Publicado: (2009)

A Compact Low-Power Driver Array for VCSELs in 65-nm CMOS Technology
por: Zeng, Zhiyao, et al.
Publicado: (2017)

A High-Resolution Clock Phase-Shifter in a 65 nm CMOS Technology
por: Yang, Dongxu, et al.
Publicado: (2018)

Design of an analog monolithic pixel sensor prototype in TPSCo 65 nm CMOS imaging technology
por: Deng, W, et al.
Publicado: (2023)

1-Grad total dose evaluation of 65 nm CMOS technology for the HL-LHC upgrades
por: Menouni, M, et al.
Publicado: (2015)

Charge sensing properties of monolithic CMOS pixel sensors fabricated in a 65 nm technology
por: Bugiel, Szymon, et al.
Publicado: (2022)

Development of monolithic sensors for high energy physics in commercial CMOS technologies
por: Snoeys, W
Publicado: (2019)

Front end electronics for silicon strip detectors in 90-nm CMOS technology: Advantages and challenges
por: Kaplon, J, et al.
Publicado: (2010)

Cannot write session to /tmp/vufind_sessions/sess_8mb846rvprghslrdgr50cu41nb