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FED firmware interface testing with pixel phase 1 emulator
A hardware emulation of the CMS pixel detector phase 1 upgrade front-end electronics has been developed to test and validate the architecture of the back-end electronics (FED) firmware. The emulation is implemented on a Virtex 6 FPGA on the CERN GLIB uTCA platform, utilizing an 8-way SFP FPGA Mezz...
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| Lenguaje: | eng |
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2017
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| Acceso en línea: | https://dx.doi.org/10.22323/1.313.0074 http://cds.cern.ch/record/2309653 |