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Design and optimisation of low power hybrid pixel array logic for the extreme hit and trigger rates of the Large Hadron Collider upgrade
Digital design of integrated circuits in nanometer technology requires to address several design challenges. Among those, system complexity has to be handled with modern techniques and tools, power density needs to be considered as a major player in design choices (trade-off versus performance), cloc...
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| Lenguaje: | eng |
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2018
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| Acceso en línea: | http://cds.cern.ch/record/2630094 |