Design and optimisation of low power hybrid pixel array logic for the extreme hit and trigger rates of the Large Hadron Collider upgrade

Digital design of integrated circuits in nanometer technology requires to address several design challenges. Among those, system complexity has to be handled with modern techniques and tools, power density needs to be considered as a major player in design choices (trade-off versus performance), clock distribution and timing closure require special attention due to large chip size (impact of interconnections) and variability issues demanding additional timing safety margins. These issues are common to multiple research and industry applications, among which the design of the readout electronics of next generation hybrid pixel detectors for the High-Luminosity Large Hadron Collider (HL-LHC) at CERN. In addition, in this application circuits operate in harsh radiation environments, experiencing performance degradation and various classes of hard/soft errors. Pixel detectors are devices capable of detecting different forms of radiation with high resolution (up to a few micrometers), thanks to the small size of the sensing element. In High Energy Physics (HEP) applications particles are detected based on their ionizing interaction with the sensor and collected information has to be readout through dedicated high density electronics. For applications demanding fast detection, tolerance of high radiation levels (above tens of Mrads), reliability with high input rates (in the order of few GHz/cm2), the sensor and the electronics are normally fabricated in separate substrates. Such a systems is referred to as Hybrid Pixel Detector (HPD). This work is part of the effort to design the digital readout electronics of next generation hybrid pixel detectors. The most relevant examples are the pixel detectors for the HEP experiments A Toroidal LHC ApparatuS (ATLAS), Compact Muon Solenoid (CMS) and A Large Ion Collider Experiment (ALICE) at the LHC. New generation pixel detector systems and ASICs for High Energy Physics (HEP) applications will be a big step forward and will have to meet specifications in terms of smaller pixels to improve tracking resolution, much higher hit rates (3GHz/cm2), much higher output bandwidth and large integrated circuits with low power consumption and low power fluctuations. Their electronics will also have to work reliably for years under the hostile radiation conditions, requiring unprecedented radiation tolerance (up to 1Grad). The PhD activity is part of the design effort to develop the digital readout electronics of such complex systems using commercial high-scaled technologies and requires to face challenges which are of common interest in the technological and scientific context, i.e. system complexity, low power consumption, reliability in hostile environments (shared also with space applications). The design of next generation pixel detector systems has driven the creation of multiple collaborations and projects, to which the PhD activity has been an active contribution: RD53, an international collaboration of universities and research institutes, targeted to design the next generation of hybrid pixel readout chips to enable the phase 2 pixel upgrades of the ATLAS (A Thoroidal LHC ApparatuS) and CMS (Compact Muon Solenoid) experiments. The readout chip, named RD53A, has been prototyped in August 2017; CHIPIX65, an Italian project born with the primary goal of developing an innovative CHIP for a PIXel detector, using a CMOS 65nm technology, for experiments with extreme particle rates and radiation (effort shared with the RD53 Collaboration). Such a chip has been prototyped in June 2016; AIDA-2020 (Advanced European Infrastructures for Detectors at Accelerators), an European project aiming at pushing detector technologies beyond the state-of-the-art and offering highly equipped infrastructures for testing.