Ultrascale+ for the new ATLAS calorimeter trigger board dedicated to jet identification

To cope with the expected increase in luminosity at the Large Hadron Collider in 2021, the ATLAS collaboration is planning a major detector upgrade to be installed during Long Shutdown 2. As a part of this, the Level 1 trigger, based on calorimeter data, will be upgraded to exploit the fine granularity readout using a new system of Feature EXtractors (FEXs), which each reconstruct different physics objects for the trigger selection. The Jet FEX (jFEX) is one of three FEXs and has been conceived to identify small/large area jets, large area tau leptons, missing transverse energy and the total sum of the transverse energy. The use of the latest generation Xilinx Field Programmable Gate Array (FPGA), the Ultrascale+, was dictated by the physics requirements which include substantial processing power and large input bandwidth, up to ˜3Tb/s, within a tight latency budget <390 ns. The jFEX board is characterised by a modular design that makes it possible to optimise within the limited space of an ATCA board a large number of high speed signals. To guarantee the signal integrity, the board design has been accompanied by simulation of the power, current and thermal distribution. The printed circuit board has a 24-layer stack-up and uses the MEGTRON6 material, commonly used for signal transmission above 10 Gb/s. This presentation focuses on the technological aspects of the jFEX board, reporting on the simulation studies and on the design solutions of the board. Two jFEX prototypes have been produced and fully tested in integrated tests at CERN, these test results will be presented. The firmware implemented on the trigger board will be illustrated in connection with the FPGA performance and board power consumption. The jFEX system, consisting of 6 boards, will be produced by end of 2018 to allow the installation and commissioning of the full system in time for the LHC restart at the beginning of 2021.