Degradation and Dose-Rate Dependence in Decananometer MOSFETs Exposed to Ultra-High Levels of Total Ionizing Dose

The main experiment performed in this thesis is called ``Low Dose-Rate Sensitivity'', an analysis conducted on 65-nm technology node, intended to be implemented in most of the circuitry for CERN HL-LHC (High Luminosity - Large Hadron Collider) upgrade. The dose-rate (DR) is the dose absorbed per unit of time. If the DR is integrated over the irradiation time, then the Total Ionizing Dose (TID) deposited is obtained. The electronic components mostly affected by ionizing radiation, belonging to CMS and ATLAS detectors, are expected to reach TIDs up to 1 Grad(SiO$_{2}$) in 10 years. The relative dose-rate is therefore around 0.01 Mrad(SiO$_{2}$)/h. In the standard radiation assurance procedures, the devices are irradiated with dose-rate in the order of 10 Mrad(SiO$_{2}$)/h, which are 1000 times higher than the real faced one. BJT are strongly sensitive to the changes in the DR, in what is called Extremely Low Dose Rate Sensitivity (ELDRS). In practice, for the same level of TID, low dose-rate experiments provoke a much more severe degradation than a high DR irradiation. Up to now, MOSFETs are supposed to be insensitive to changes in the dose-rate. We demonstrated with a set of experiments that this dose-rate dependency is found also in the modern transistors. We obtained interesting results regarding bias and temperature dependencies. In addition, we used both an experimental and modeling approach, developing a coherent model that takes into account the differences between high and low dose-rates mechanisms. The results obtained will be the starting point for future studies and will be used for scientific publications. We conducted experiments on the 28 nm technology node, which can represent a good alternative for CERN applications. In fact, as previously mentioned in other recent papers, this technology is particularly strong against ionizing dose. We irradiated up to 1 Grad(SiO$_{2}$) a set of devices, and we encountered output current percentage degradation of nearly 10%. This is an encouraging result since, compared to previous technology nodes like the 130 nm or even the 65 nm, the same parameter was reduced by approximately 70%. As a notable draw-back, this new technology is strongly affected by drastic increases in the leakage current. These rises provoke enhancement in the static power dissipation of the circuits, which is intolerable in most modern applications.