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Test generation of crosstalk delay faults in VLSI circuits

Detalles Bibliográficos
Autores principales:	Jayanthy, S, Bhuvaneswari, M C
Lenguaje:	eng
Publicado:	Springer 2018
Materias:	Engineering
Acceso en línea:	http://cds.cern.ch/record/2710614

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