The Prototype Hardware Design of Global Common Module for Global Trigger System of the ATLAS Phase-II Upgrade on HL-LHC

The HL-LHC [1] is expected to start operations in the middle of 2027, to deliver more than ten times the integrated luminosity of the LHC Runs 1-3 combined (up to 4000 fb−1). Meeting these requirements poses significant challenges to the hardware design of Trigger and Data Acquisition system. A baseline architecture, based on a single-level hardware trigger with a maximum rate of 1 MHz and 10 µs latency, is proposed for ATLAS. The hardware-based Level-0 Trigger system is composed of the Level-0 Calorimeter Trigger (L0Calo) [2], the Level-0 Muon Trigger (L0Muon) [3], the Global Trigger [4] and the Central Trigger sub-systems [4]. The Global Trigger is a new subsystem, which will perform offline-like algorithms on full-granularity calorimeter data. The calorimeter detector subsystems, FEXs [3], and MUCTPI [3] provide serial data for each bunch crossing to the MUX layer. These signals are then time-multiplexed [5] and the signals for a given event are transported to a single GEP node that executes the algorithms. The results are then sent to the CTP through the CTP Interface. The hardware implementation of the Global Trigger consists of three primary components: a Multiplexer Processor (MUX) layer, a GEP layer, and a demultiplexing Global-to-CTP Interface (CTP Interface), all of which have identical hardware composed of ATCA modules and FPGAs with many multi-gigabit transceivers. The single Global Common Module (GCM) hardware is implemented across the Global Trigger system, minimizing the complexity of the firmware and simplifying the system design and long-term maintenance.