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SystemVerilog for design: a guide to using systemverilog for hardware design and modeling

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Detalles Bibliográficos
Autores principales:	Sutherland, Stuart, Davidmann, Simon, Flake, Peter
Lenguaje:	eng
Publicado:	Springer 2003
Materias:	XX
Acceso en línea:	http://cds.cern.ch/record/2756801

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