Effects of Bias and Temperature on the Dose-Rate Sensitivity of 65-nm CMOS Transistors

MOS transistors in 65-nm CMOS technology exposed to ultrahigh total ionizing dose (TID) levels show clear evidence of a true dose-rate (DR) dependence. In order to assess the impact of this effect and to understand its origin, an extensive measurement campaign has been carried out at different DRs, different temperatures, and different biases. Both nMOS and pMOS devices with different sizes and geometries were studied. The results obtained clearly show that the DR sensitivity of these devices is due to mechanisms that occur in the spacer insulators. Spacers have only recently been identified as an important element in the radiation response of MOS devices exposed to ultrahigh doses and the mechanisms causing their DR sensitivity appear to be largely compatible with the models developed to explain enhanced low dose-rate sensitivity (ELDRS) in linear bipolar transistors.