Low-power SEE hardening techniques and error rate evaluation in 65 nm readout ASICs

Single event radiation effects represent one of the main challenges for digital designs exposed to ionizing particles in high energy physics detectors. Radiation hardening techniques are based on redundancy, leading to a significant increase in power consumption and area overhead. This contribution will present the single event effects hardening techniques adopted in the pixel and strip readout ASICs of the PS modules for the CMS outer tracker upgrade in relation to power requirements and error rates. Cross section measurements on the silicon prototypes and expected error rates evaluated for the CMS tracker particle flux and spectrum will be presented.