Implementation and testing of Design For Testability methodologies in 65 nm ASICs for HL-LHC.

<!--HTML-->The development of the MPA and SSA ASICs is approaching the production phase with a volume of more than 1000 wafers. The importance of yield management in the construction of the Outer Tracker modules requires rigorous testing methods capable to identify all defective parts. This contribution presents customized Design for Testability methods to replace the currently used functional tests that show limited coverage and long testing time. Scan-chain design, memory and Logic Built-In-Self-Test have been adapted for radiation-hard ASICs and introduced on-chip for a novel testing approach. Design flow and implementation choices will be presented together with silicon results.